A Fast Evaluation Approach of Data Consistency Protocols within a Compilation Toolchain

International audienceShared memory is a critical issue for large distributed systems. Despite several data consistency protocols have been proposed, the selection of the protocol that best suits to the application requirements and system constraints remains a challenge. The development of multi-consistency systems, where different protocols can be deployed during runtime, appears to be an interesting alternative. In order to explore the design space of the consistency protocols a fast and accurate method should be used. In this work we rely on a compilation toolchain that transparently handles data consistency decisions for a multi-protocol platform. We focus on the analytical evaluation of the consistency configuration that stands within the optimization loop. We propose to use a TLM NoC simulator to get feedback on expected network contentions. We evaluate the approach using five workloads and three different data consistency protocols. As a result, we are able to obtain a fast and accurate evaluation of the different consistency alternatives

Side-Channel Protected MPSoC through Secure Real-Time Networks-on-Chip

The integration of Multi-Processors System-on-Chip (MPSoCs) into the Internet -of -Things (IoT) context brings new opportunities, but also represent risks. Tight real-time constraints and security requirements should be considered simultaneously when designing MPSoCs. Network-on-Chip (NoCs) are specially critical when meeting these two conflicting characteristics. For instance the NoC design has a huge influence in the security of the system. A vital threat to system security are so-called side-channel attacks based on the NoC communication observations. To this end, we propose a NoC security mechanism suitable for hard real-time systems, in which schedulability is a vital design requirement. We present three contributions. First, we show the impact of the NoC routing in the security of the system. Second, we propose a packet route randomisation mechanism to increase NoC resilience against side-channel attacks. Third, using an evolutionary optimisation approach, we effectively apply route randomisation while controlling its impact on hard real-time performance guarantees. Extensive experimental evidence based on analytical and simulation models supports our findings

Reconfigurable Security Architecture for disrupted protection zones in NoC−Based MPSoCs

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3D-LeukoNoC: A Dynamic TSV-Based 3D-MPSoC Protection

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Protection of heterogeneous architectures on FPGAs: An approach based on hardware firewalls

International audienceEmbedded systems are parts of our daily life and used in many fields. They can be found in smart-phones or in modern cars including GPS, light/rain sensors and other electronic assistance mechanisms.These systems may handle sensitive data (such as credit card numbers, critical information about thehost system and so on) which must be protected against external attacks as these data may be transmit-ted through a communication link where attackers can connect to extract sensitive information or injectmalicious code within the system. This work presents an approach to protect communications in multi-processor architectures. This approach is based on hardware security enhancements acting as firewalls.These firewalls filter all data going through the system communication bus and an additional flexiblecryptographic block aims to protect external memory from attacks. Benefits of our approach are demon-strated using a case study and some custom software applications implemented in a Field-ProgrammableGate Array (FPGA). Firewalls implemented in the target architecture allow getting a low-latency securitylayer with flexible cryptographic features. To illustrate the benefit of such a solution, implementations arediscussed for different MPSoCs implemented on Xilinx Virtex-6 FPGAs. Results demonstrate a reductionup to 33% in terms of latency overhead compared to existing effort

Theatre and Architecture - Stage Design - Costume. A Bibliographic guide in five languages (1970-2000)

Security can be seen as an optimisation objective in NoC resource management, and as such poses trade-offs against other objectives such as real-time schedulability. In this paper, we show how to increase NoC resilience against a concrete type of security attack, named side-channel attack, which exploit the correlation between specific non-functional properties (such as packet latencies and routes, in the case of NoCs) to infer the functional behaviour of secure applications. For instance, the transmission of a packet over a given link of the NoC may hint on a cache miss, which can be used by an attacker to guess specific parts of a secret cryptographic key, effectively weakening it. We therefore propose packet route randomisation as a mechanism to increase NoC resilience against side-channel attacks, focusing specifically on the potential impact of such an approach upon hard real-time systems, where schedulability is a vital design requirement. Using an evolutionary optimisation approach, we show how to effectively apply route randomisation in such a way that it can increase NoC security while controlling its impact on hard real-time performance guarantees. Extensive experimental evidence based on analytical and simulation models supports our findings

A multi-objective adaptive immune algorithm for multi-application NoC mapping

International audienceCurrent SoC design trends are characterized by the integration of larger amount of IPs targeting a wide range of application fields. Such multi-application systems are constrained by a set of requirements. In such scenario network-on-chips (NoC) are becoming more important as the on-chip communication structure. Designing an optimal NoC for satisfying the requirements of each individual application requires the specification of a large set of configuration parameters leading to a wide solution space. It has been shown that IP mapping is one of the most critical parameters in NoC design, strongly influencing the SoC performance. IP mapping has been solved for single application systems using single and multi-objective optimization algorithms. In this paper we propose the use of a multi-objective adaptive immune algorithm (M(2)AIA), an evolutionary approach to solve the multi-application NoC mapping problem. Latency and power consumption were adopted as the target multi-objective functions. To compare the efficiency of our approach, our results are compared with those of the genetic and branch and bound multi-objective mapping algorithms. We tested 11 well-known benchmarks, including random and real applications, and combines up to 8 applications at the same SoC. The experimental results showed that the M(2)AIA decreases in average the power consumption and the latency 27.3 and 42.1 % compared to the branch and bound approach and 29.3 and 36.1 % over the genetic approach

NoC-Based Protection for SoC Time-Driven Attacks

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Network Contention-Aware Method to Evaluate Data Coherency Protocols within a Compilation Toolchain

International audienceShared memory is a critical issue for large distributed systems. Despite several data coherency protocols have been proposed, the selection of the protocol that best suits to the application requirements and system constraints remains a challenge. The development of multi-coherency systems, where different protocols can be deployed during runtime, appears to be an interesting alternative. In order to explore the design space of the coherency protocols a fast and accurate method should be used. In this work we rely on a compilation toolchain that transparently handles data coherency decisions for a multi-protocol platform. We focus on the analytical evaluation of the coherency configuration that stands within the optimization loop. We propose to use a TLM NoC simulator to get feedback on expected network contentions. We evaluate the approach using five workloads, three data coherency protocols and two NoC topologies. As a result, we are able to obtain a fast and accurate evaluation of the different coherency-protocol alternatives

Notifying Memories: a case-study on Data-Flow Applications with NoC Interfaces Implementation

International audienceNoC-based architectures overcome the limitations of traditional buses by exploiting parallelism and offer large band-widths. NoC adoption also increases communication la-tency, which is especially penalising for data-flow applications (DF). We introduce the notifying memories (NM) concept to reduce this overhead. Our original approach eliminates useless memory requests. This paper demonstrates NM in the context of video coding applications implemented with dynamic DF. We have conducted cycle accurate sys-temC simulation of the NoC on an MPEG4 decoder to evaluate NM efficiency. The results show significant reductions in terms of latency (78%), injection rate (60%), and power savings (49%) along with throughput improvement (16%)